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SL28PCIe16

EProClock

PCI Express Gen 2 & Gen 3 Clock Generator

Features

• Optimized 100 MHz Operating Frequencies to Meet the

Next Generation PCI-Express Gen 2 & Gen 3

• Low power push-pull type differential output buffers

• Integrated voltage regulator

• Integrated resistors on differential clocks

• Six 100-MHz differential SRC clocks

• Low jitter (<50ps)

• 25MHz Crystal Input or Clock input

• EProClock

Programmable Technology

• I

C support with readback capabilities

• Triangular Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• Industrial Temperature -40

C to 85

• 3.3V Power supply

• 32-pin QFN package

Block Diagram

Pin Configuration

XIN

XOUT

Crystal/

CLKIN

PLL 1

(SSC)

Divider

SRC [5:0]

EProClock

Technology

SCLK

SDATA

Logic

Core

DOC#: SP-AP-0790 (Rev. 0.3)

400 West Cesar Chavez, Austin, TX 78701

1+(512) 416-8500

1+(512) 416-9669

Page 1 of 12

www.silabs.com

SL28PCIe16

32-QFN Pin Definitions

Pin No.

Name

VDD_SRC

VSS

SRC0

SRC0#

VDD_SRC

SRC1

SRC1#

SRC2

SRC2#

VSS_SRC

VDD_SRC

SRC3#

SRC3

SRC4#

SRC4

VDD_SRC

SRC5#

SRC5

VSS_SRC

SCLK

SDATA

XOUT

XIN / CLKIN

VSS_CORE

VDD_CORE

VDD_SRC

VSS_SRC

Type

PWR

GND

Description

3.3V Power Supply

No Connect.

Ground

O, DIF 100MHz True differential serial reference clock

O, DIF 100MHz Complement differential serial reference clock

PWR

3.3V Power Supply

O, DIF 100MHz True differential serial reference clock

O, DIF 100MHz Complement differential serial reference clock

O, DIF 100MHz True differential serial reference clock

O, DIF 100MHz Complement differential serial reference clock

GND

PWR

Ground

3.3V Power Supply

O, DIF 100MHz Complement differential serial reference clock

O, DIF 100MHz True differential serial reference clock

O, DIF 100MHz Complement differential serial reference clock

O, DIF 100MHz True differential serial reference clock

PWR

3.3V Power Supply

O, DIF 100MHz Complement differential serial reference clock

O, DIF 100MHz True differential serial reference clock

GND

I/O

GND

PWR

GND

Ground

SMBus compatible SCLOCK

SMBus compatible SDATA

25.00MHz Crystal output,

Float XOUT if using only CLKIN (Clock input)

25.00MHz Crystal input or 3.3V, 25MHz Clock Input

Ground

No Connect.

3.3V Power Supply

No Connect.

Ground

EProClock

Programmable Technology

EProClock

is the world’s first non-volatile programmable

clock. The EProClock

technology allows board designer to

promptly achieve optimum compliance and clock signal

integrity; historically, attainable typically through device and/or

board redesigns.

hard coded.

Features:

- > 4000 bits of configurations

- Can be configured through SMBus or hard coded

- Custom frequency sets

DOC#: SP-AP-0790 (Rev. 0.3)

Page 2 of 12

EProClock

technology can be configured through SMBus or

- Differential skew control on true or compliment or both

- Differential duty cycle control on true or compliment or both

- Differential amplitude control

- Differential and single-ended slew rate control

- Program Internal or External series resistor on single-ended

clocks

- Program different spread profiles

- Program different spread modulation rate

SL28PCIe16

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers are individually enabled or disabled. The

registers associated with the Serial Data Interface initialize to

their default setting at power-up. The use of this interface is

optional. Clock device register changes are normally made at

system initialization, if any are required. The interface cannot

be used during system operation for power management

functions.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, access the bytes in sequential

order from lowest to highest (most significant bit first) with the

ability to stop after any complete byte is transferred. For byte

write and byte read operations, the system controller can

access individually indexed bytes. The offset of the indexed

byte is encoded in the command code described in

Table 1.

The block write and block read protocol is outlined in

Table 2

while

Table 3

outlines byte write and byte read protocol. The

slave receiver address is 11010010 (D2h).

Table 1. Command Code Definition

Bit

(6:0)

Description

0 = Block read or block write operation, 1 = Byte read or byte write operation

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Bit

8:2

18:11

27:20

36:29

45:38

....

Start

Slave address–7 bits

Write

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Byte Count–8 bits

Acknowledge from slave

Data byte 1–8 bits

Acknowledge from slave

Data byte 2–8 bits

Acknowledge from slave

Data Byte /Slave Acknowledges

Data Byte N–8 bits

Acknowledge from slave

Stop

Description

Bit

8:2

18:11

27:21

37:30

46:39

55:48

....

Start

Slave address–7 bits

Write

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeat start

Slave address–7 bits

Read = 1

Acknowledge from slave

Byte Count from slave–8 bits

Acknowledge

Data byte 1 from slave–8 bits

Acknowledge

Data byte 2 from slave–8 bits

Acknowledge

Data bytes from slave / Acknowledge

Data Byte N from slave–8 bits

NOT Acknowledge

Stop

Block Read Protocol

Description

Control Registers

Table 3. Byte Read and Byte Write Protocol

Byte Write Protocol

Bit

Start

Description

Bit

Start

Byte Read Protocol

Description

DOC#: SP-AP-0790 (Rev. 0.3)

Page 3 of 12

SL28PCIe16

Table 3. Byte Read and Byte Write Protocol

8:2

18:11

27:20

Slave address–7 bits

Write

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Data byte–8 bits

Acknowledge from slave

Stop

8:2

18:11

27:21

37:30

Byte 0: Control Register 0

Bit

@Pup

Name

RESERVED

Spread Enable

RESERVED

Enable spread for SRC outputs

0=Disable, 1= -0.5%

RESERVED

Description

Slave address–7 bits

Write

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeated start

Slave address–7 bits

Read

Acknowledge from slave

Data from slave–8 bits

NOT Acknowledge

Stop

Byte 1: Control Register 1

Bit

@Pup

Name

RESERVED

SRC0_OE

RESERVED

SRC1_OE

RESERVED

Output enable for SRC0

0 = Output Disabled, 1 = Output Enabled

RESERVED

Output enable for SRC1

0 = Output Disabled, 1 = Output Enabled

RESERVED

Description

Byte 2: Control Register 2

Bit

@Pup

Name

RESERVED

Description

DOC#: SP-AP-0790 (Rev. 0.3)

Page 4 of 12

SL28PCIe16

Byte 2: Control Register 2

(continued)

Bit

@Pup

Name

RESERVED

Description

Byte 3: Control Register 3

Bit

@Pup

Name

SRC4_OE

SRC5_OE

RESERVED

Description

Output enable for SRC4

0 = Output Disabled, 1 = Output Enabled

Output enable for SRC5

0 = Output Disabled, 1 = Output Enabled

RESERVED

Byte 4: Control Register 4

Bit

@Pup

Name

RESERVED

Description

Byte 5: Control Register 5

Bit

@Pup

Name

RESERVED

Description

Byte 6: Control Register 6

Bit

@Pup

Name

SRC[5:4]_AMP1

SRC[5:4]_AMP0

Description

SRC[5:4] amplitude adjustment

00= 700mV, 01=800mV, 10=900mV, 11= 1000mV

DOC#: SP-AP-0790 (Rev. 0.3)

Page 5 of 12

型号	SL28PCIe16LIT	SL28PCIe16LCT	SL28PCIe16LC
描述	clock generators & support products 6output pcie G3 from 25mhz input	clock generators & support products 6output pcie G3 from 25mhz input	clock generators & support products 6output pcie G3 from 25mhz input
Manufacture	Silicon Laboratories	Silicon Laboratories	Silicon Laboratories
产品种类 Product Category	Clock Generators & Support Products	Clock Generators & Support Products	Clock Generators & Support Products
RoHS	Yes	Yes	Yes
类型 Type	Clock Generators	Clock Generators	Clock Generators
系列 Packaging	Reel	Reel	Bulk
工厂包装数量 Factory Pack Quantity	2500	2500	624